Webinars
Upcoming Webinar
A Deep Dive into UCIe-3D
Wednesday, December 4, 2024 at 8 AM PT / 11 AM ET
With increasing demands for higher performance, bandwidth density, and power efficiency the industry is rapidly adopting 2.5D and 3D packaging technologies to address these challenges. This shift highlights the pressing need for a unified industry ecosystem standard—one that provides a standardized architecture for streamlined manageability and addresses the unique design complexities of advanced packaging. The UCIe 2.0 specification supports 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures.
Join us in this webinar as we dive into the benefits of UCIe-3D including its hybrid bonding optimization, flexible bump pitch adaptability, and the scalability needed to drive the next wave of chiplet and packaging innovations.
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Presenter:
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Zuoguo (Joe) Wu, UCIe Consortium Electrical Working Group Co-Chair and Sr Principal Engineer at Intel
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Register for the webinar here.
Webinar Recordings
Introducing the UCIe™ 2.0 Specification: Supporting 3D Packaging and Manageability System Architecture
Aired: September 19, 2024
Exploring the Advancement of Chiplet Technology and the Ecosystem
Aired: April 17, 2024
The UCIe™ (Universal Chiplet Interconnect Express™) 2.0 Specification was released in August 2024, adding support for a standardized system architecture for manageability and holistically addresses the design challenges for testability, manageability, and debug (DFx) for the SIP lifecycle across multiple chiplets – from sort to management in the field.
The webinar will explore the new features in the UCIe 2.0 specification including support for 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. The webinar will also introduce optional manageability features and a UCIe DFx Architecture (UDA), which includes a management fabric within each chiplet for testing, telemetry, and debug functions. It also enables vendor agnostic chiplet interoperability across a flexible and unified approach to SIP management and DFx operations.
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Presenter:
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Dr. Debendra Das Sharma, UCIe Consortium Chairman, and Intel Senior Fellow and co-GM Memory
and I/O Technologies, Intel Corporation​
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Download the webinar presentation here.
Semiconductor companies are making transistors smaller and cramming more into chips to meet the demands of today’s high-tech industries and applications. In fact, in a recent article from the Financial Times, technology industry consultants McKinsey forecast that semiconductors will become a trillion-dollar industry by the end of this decade. Even with this massive growth, manufacturers recognize the need to balance costs with chip performance and are working to solve this challenge by shifting toward chiplet manufacturing – creating smaller, modular chiplets, designed for a specific function, that can be connected to build a larger system. Chiplets enable design flexibility for end-users seeking to match chip designs based on requirements.
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UCIe™ (Universal Chiplet Interconnect Express™) provides an industry standard for interface and is driving the adoption of chiplet technology. The open specification defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.
This webinar aims to explore the industry trends that prompted the development of chiplet technology and how an interoperable solution meets industry demand. Our panelists will also discuss how UCIe fosters collaboration in the industry toward the future of chiplet innovation in markets such as AI, ML, aerospace, and automotive.
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Moderator: Brian Rea (UCIe Consortium Marketing Workgroup Chair, Intel)
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Panelists: Ericles Rodrigues Sousa (Cadence Design Systems), Hee-Soo Lee (Keysight Technologies, EDA), and Saman Sadr (Neuron IP)
The UCIe™ 1.1 Specification:
Future Applications of Chiplets
Aired: October 12, 2023
The UCIe™ (Universal Chiplet Interconnect Express™) 1.1 Specification was released in August 2023, delivering valuable improvements to the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models.
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This webinar provides an overview of enhancements made in the UCIe 1.1 specification and architectural specification attributes to define system setups and registers used in test plans and compliance testing to ensure device interoperability. The presentation will also explore additional enhancements for automotive usages – such as predictive failure analysis and health monitoring – and enabling lower-cost packaging implementations.
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Presenter:
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Dr. Debendra Das Sharma, UCIe Consortium Chairman, and Intel Senior Fellow and co-GM Memory
and I/O Technologies, Intel Corporation
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Download the webinar presentation here.
UCIe™ Packaging Technologies
Aired: Thursday, June 15, 2023
UCIe™ (Universal Chiplet Interconnect Express™) is an open specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.
UCIe technology offers flexibility for integration across multiple packaging technologies. The webinar will cover standard laminate as well as advanced options such as silicon interposers, silicon bridges, and fan-out/RDL from multiple vendors. The presentation will also explore the 2D and 2.5D physical bump map arrangements along with interoperability rules. Attendees will have a chance to participate in a live Q&A discussion immediately after the webinar to address questions from the presentation.
Presenters:
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Gerald Pasdast, UCIe Consortium Form Factor and Compliance Workgroup Co-Chair and Senior Principal Engineer at Intel
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Stefan Rusu, Senior Director at TSMC
Introduction to UCIe™
Aired: Tuesday, February 21, 2023
UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers to address customer requests for more customizable package-level integration. The newly formed UCIe Consortium fosters an open chiplet ecosystem by offering high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity between chiplets.
This educational webinar is brought to you by the UCIe Consortium and presented by Dr. Debendra Das Sharma, Chairman of the UCIe Consortium. The webinar will explore the industry demands and developments that brought about the need for a UCIe specification and share how end-users can easily mix and match chiplet components provided by a multi-vendor ecosystem for System-on-Chip (SoC) construction — including customized SoC.
Download the webinar presentation here.