The semiconductor industry is on the brink of a transformative era, driven by the need for higher performance, greater efficiency, and more flexible design methodologies. At the heart of this transformation is the Universal Chiplet Interconnect Express™ (UCIe™), a groundbreaking standard that promises to revolutionize the way we design and integrate chiplets. A tutorial session hosted by UCIe Consortium at the 2025 Chiplet Summit brought together industry leaders and experts from Arm, Alphawave Semi, AMD, Cadence, Siemens, and Ayar Labs to discuss the strengths, opportunities, and future directions of UCIe. This blog post recaps the key insights and takeaways from the UCIe member’s tutorials, highlighting the positive impact UCIe is already making on the semiconductor landscape.
The Promise of UCIe: Standardization and Interoperability
One of the most compelling aspects of UCIe is its ability to provide a standardized interface for chiplets, promoting interoperability between components from different vendors. Mark Knight from Arm kicked off the tutorial by emphasizing the importance of defining interface requirements for chiplets. Arm highlighted that standardization reduces complexity and integration risks, making it easier for designers to create innovative solutions. He highlighted that the industry should avoid fragmentation of approaches which will be a barrier to interoperability and re-use needed to achieve a robust chiplet economy.
Mark announced that the Arm "CSA" or "Chiplet System Architecture" Specification 1.0 beta 0 is now available for public download, with over 60 partners already engaged. It includes topology, partitioning, memory traffic, device configuration, interrupts, and trace. Future versions will address critical issues such as security, boot image security, counter synchronization, system control, and dynamic discovery of chiplets. By providing a clear roadmap for development, Arm is helping to pave the way for the widespread adoption of UCIe.
Leveraging Chiplets for Efficiency and Scalability
Sue Hung Fung from Alphawave Semi provided an insightful look into how chiplets are being leveraged for more efficient and scalable system-in-package (SiP) solutions. Chiplets are crucial to support the architectures in development to address AI workloads as monolithic dies reach reticle size limits. By reusing chiplets, customers can create cost-effective solutions that are highly customizable.
Alphawave Semi's portfolio includes both high speed interface IP subsystems and the new AlphaCHIP1600-I/O chiplet which provides UCIe PHY/Controller IP, Ethernet and PCIe/CXL Subsystems to achieve up to 1.6Tbps throughput at MR, XLR, and PCIe/CXL reach. Sue also discussed the exciting progress towards optical chiplet enablement, demonstrating co-packaged copper and planning near-packaged and co-packaged optics. This move towards optical chiplets promises to deliver significant power efficiency and performance benefits, further enhancing the capabilities of UCIe.
Sue shared several use case examples including the AlphaCHIP1600 IO Chiplet Extension off of an accelerator die. The accelerator is connected to Alphawave Semi's Arm Neoverse Compute Chiplet, based on Arm's Compute SubSystems (CSS). Additional use cases included 100Terabit switches utilizing chiplets, AI acceleration, and Optical chiplet enablement.
Integrating RF Chiplets for Small Form Factor Devices
Millind Mittal from AMD shared a concept for integrating RF chiplets with FPGA or ASICs for small form factor devices. This integration is crucial for applications that require compact, high-performance solutions. Milind emphasized the need for standardized chiplet interfaces, which UCIe provides, to ensure seamless communication and interoperability.
AMD is actively involved in government-funded projects to create a UCIe-based ecosystem for RF integration. This involvement underscores the importance of UCIe in enabling advanced applications and fostering innovation. Milind also highlighted the importance of reliability and synchronization in chiplet communication, leveraging UCIe's defined interfaces and reliability mechanisms to achieve robust performance.
Building a Chiplet Framework for Simplified Construction
Junie Um from Cadence emphasized the importance of a chiplet framework for simplifying construction and automating the design process. Cadence is working on a reference platform that includes CPU, system, and AI chiplets, using UCIe for standard data interfaces. This approach ensures that chiplets can be easily integrated into a cohesive system, reducing development time and effort.
Cadence's focus on system-level control, security, and safety is critical for ensuring interoperability and standardization across chiplets. By addressing these aspects, Cadence is helping to create a robust ecosystem that supports the widespread adoption of UCIe. Junie also discussed the importance of system-level integration, including power management, thermal management, and system control, to ensure the success of UCIe-based solutions.
Verification and Compliance Testing
Kevin Jennings from Cadence highlighted the successful collaboration with Intel to achieve UCIe compliance and interoperability testing through pre-silicon simulation, identifying additional RTL features for future IP versions. Finding issues before silicon powers on is highly valuable, even more so with chiplets compared to pluggable chip or card-based solutions.
Justin Bunnell from Siemens provided an overview of Siemens' efforts to develop verification IP for UCIe, enabling compliance and interoperability testing in simulation. Siemens has conducted a pilot project with Alphawave Semi and Ayar Labs, integrating their IPs and using Siemens' verification IP for testing. This collaboration highlights the importance of early interoperability testing to ensure that chiplets can work seamlessly together.
Justin emphasized the need for robust compliance and interoperability testing frameworks, which are essential for reducing tapeout risks and ensuring reliable performance. Siemens' verification IP supports the latest UCIe features, including manageability and debug capabilities, providing a comprehensive solution for developers. By addressing these areas, Siemens is helping to build confidence in UCIe and accelerate its adoption.
Optical IO Chiplets: A Game-Changer for AI and High-Performance Applications
LK Bhupathi from Ayar Labs discussed the transformative potential of optical IO chiplets, which promise to deliver high bandwidth, low latency, reach and power-efficient connectivity solutions required for AI innovation and application growth. Ayar Labs' roadmap includes UCIe-compliant TeraPHY™ optical I/O chiplets, allowing them to connect seamlessly with other UCIe-compliant devices. This standardization is crucial for promoting interoperability and ease of integration.
LK showcased a live demonstration of Ayar Labs’ optical I/O chiplets integrated with an FPGA, highlighting the practical implementation and readiness of their technology. Ayar Labs is actively working on ecosystem development, collaborating with partners to deliver known good die (KGD) chiplets and laser modules. This collaboration is essential for creating a robust supply chain and ensuring the success of optical I/O chiplets.
Addressing Areas of Concern for UCIe
While the strengths of UCIe are clear, the tutorials also highlighted several areas of concern that need to be addressed to ensure its success. One of the primary concerns is the need for robust compliance and interoperability testing frameworks. Kevin from Cadence and Justin from Siemens discussed the importance of establishing compliance labs and plugfests to ensure that different chiplets can work seamlessly together.
Another critical area is the enhancement of manageability and debug features. AMD and Siemens emphasized the need to standardize management protocols, error handling, and security features to ensure the reliable and secure operation of chiplet-based systems. This standardization is essential for building confidence in UCIe and ensuring its widespread adoption.
System-level integration is another area that requires attention. Junie from Cadence highlighted the importance of addressing power management, thermal management, and system control to ensure the success of UCIe-based solutions. By providing clear guidelines for system-level integration, the industry can ensure that chiplets can be easily integrated into cohesive systems.
Latency and synchronization are also critical concerns. Ensuring low latency and proper synchronization between chiplets is essential for many applications. AMD and Ayar Labs discussed the importance of addressing potential latency issues and providing mechanisms for synchronization across chiplet boundaries.
Finally, the maturity of the UCIe ecosystem is a key factor in its success. While the ecosystem is growing, it is still in its early stages. Continued collaboration and investment from industry players are needed to mature the ecosystem, develop more UCIe-compliant chiplets, and create a robust supply chain.
Conclusion: A Bright Future for UCIe
The UCIe tutorial sessions provided a comprehensive overview of the strengths and opportunities of UCIe, as well as the areas that need to be addressed to ensure ensuring an open and interoperable chiplet marketplace that enables end users to easily mix and match chiplet components from a multi-vendor ecosystem. The positive tone of the discussions highlighted the transformative potential of UCIe in the semiconductor industry. By providing a standardized interface for chiplets, UCIe promotes interoperability, reduces complexity, and enables innovative solutions.
The collaboration between industry leaders, as demonstrated by the speakers from Arm, Alphawave Semi, AMD, Cadence, Siemens, and Ayar Labs, underscores the importance of working together to build a robust ecosystem. By addressing the areas of concern and continuing to invest in the development of UCIe, the industry can unlock new levels of performance, efficiency, and innovation.
As we look to the future, the promise of UCIe is clear. With its ability to support high bandwidth, low latency, and power-efficient communication, UCIe is poised to revolutionize the way we design and integrate chiplets. The positive momentum generated by these UCIe tutorials from industry leaders in semiconductors, packaging, and IP suppliers is a testament to the bright future that lies ahead for this groundbreaking standard.