Introduction to Chiplets: Why the Industry is Moving Beyond Monolithic Designs

Author: Mayank Bhatnagar, Product Marketing Director, Cadence Design Systems

The semiconductor industry has long been driven by the pursuit of smaller, faster, and more powerful chips. However, as we approach the limits of Moore's Law, a new paradigm is emerging: chiplets. In this blog, we will explore why the industry is moving beyond monolithic design and adopting chiplets.

What are Chiplets?

Chiplets are small, modular pieces of silicon that contain a specific function or set of functions. They are designed to be combined with other chiplets to create a larger, more complex system-in-package (SiP). The interconnection between the various chiplets can be done using traces on the package substrate, called standard package routing, or through an interposer using RDL (Redistribution Layers) or silicon traces, called advanced package routing. These interconnects are called 2D or 2.5D routing as the chiplets are placed side by side facing in the same direction (usually towards the package).

Figure 1: Examples of chiplet-to-chiplet routing. Source: https://www.uciexpress.org/specification

The pitch for standard package connection fall in the 100um to 150um range. The advanced package provides much finer pitches of 25 um to 55 um. It is also possible to use connection pitches between these ranges.

Chiplets can also be connected in a 2D stack with connections made at a pitch as low as 1 um, though currently 5-25 um is more common. The chiplets can either face each other (F2F) connecting the top metals with an abutment, as shown in figure 2, or both face down (F2B), or both face away with the top metals on opposite ends of the 3D stack (B2B).

Figure 2: Example of a 3D Chiplet connection. Face-to-face interface shown. Source: https://www.uciexpress.org/specification

3D connections allow much finer interconnect pitch, with lower latency and power, but more involved power delivery and management of thermal issues and crosstalk.

Why Chiplets?

The idea of disaggregating IC (Integrated Circuit) design into smaller modular pieces has been around for a long time. However, due to various reasons, it has recently gained mainstream attention.

Reticle Size and Yield Issues

We can break this up into two sub-categories. One is the reticle limit. If your design needs more transistors that you can fit on one die, whose size is limited by the reticle limit, there is no option but to split the design across multiple dies and connect them within the package. This is becoming a larger concern as artificial intelligence and machine learning need more compute power to process the large language models. Chiplets allow designers to work around reticle constraints by creating modular, scalable compute units.

However, even before the reticle limit is reached, dropping yields can make most users think of disaggregating the design. Let’s exemplify with some hypothetical numbers to help drive home the point, without getting bogged down by specifics (and math). Every fabrication process has a possibility of random defects. Let us assume there is a 0.1% chance of defect in a 1 mm x 1 mm area of die. This means a design of this size will have a 99.9% yield. Great! Now, imagine the design grows. As it becomes a 10mm x 10mm design, which is 100mm2, the probability of a defect-free die (random defects are independent events) drops to 90.48%. At 20mm x 20mm, which is 400mm2, this yield drops to 67%, which means one out of every 3 dies manufactured have a defect and cannot be used. Breaking big monolithic dies into smaller chiplets improves yields by reducing the impact of defects, so if one chiplet has a flaw, it can be discarded without wasting the entire chip.

By using chiplets, designers can significantly improve overall yields. A defect in one small chiplet doesn’t mean a large section across a die is lost; only the flawed chiplet needs to be replaced, while the others are still usable. This smarter approach to chip design not only reduces waste but also leads to more functional products from each manufacturing run, resulting in a major business advantage.

Picking the Right Combination of Nodes – Optimizing Transistor Cost

The cost per transistor is determined by the area it occupies and the wafer cost. Traditionally, this scaled down to 69% with each process node, making it more cost-effective to move the entire design to a newer node as it became available.

Figure 3: Scaling of Cost per Transistor: Keynote by Boyd Phelps at Chiplet Summit 2025

However, as we see in Figure 3, in the latest process nodes, the cost per transistor is rising, not falling. This means there is no advantage to moving an entire design to a newer node and paying new design costs for components that do not benefit from the better performance of the new node. It is better to optimize the design for transistor (and design) cost by keeping components, such as RF analog, on older nodes and only moving performance-critical portions, such as the GPU, to the newer nodes. This is only possible if the design is disaggregated into chiplets, allowing each chiplet to use the process node that optimizes performance and cost.

Package Technology Improvements

A big hindrance to chiplet-based designs has been the need for complex packaging technology, which came with low yields and high costs. Package technology has made major advancements over the last few years, leading to lower costs, increased capacity, and significantly improved yields. In addition, options such as 2.5D and 3D advanced packaging options, previously thought too complex or risky, are now viable. These advancements have reduced the barrier to adopting chiplet-based designs.

Modular and Scalable Design

Meeting AI needs increasingly requires specialized custom silicon. For example, in training applications, you will need high-bandwidth GPU-to-GPU links that exchange weights to accelerate training and build models. A data mining application requires larger memory configurations with higher connectivity to find patterns in data. A graph analysis system, such as a navigation system, needs high-bandwidth memory to find connections between nodes. At the same time, design costs are rapidly increasing.

How do you reconcile these high costs with increased customization when fewer units of your design will sell? One way is to break the design into modular units and use chiplets to make it. This way, a single chiplet design can be used across multiple System-in-Package (SIP) designs and amortize its costs while also enabling rapid scaling and faster time to market to meet the customization needs.

Figure 4: Silicon Design is Increasingly Expensive and Custom: Presentation by Mayank Bhatnagar at FMS 2025

Optimizations for Performance, Power, and Cost

When a design is made on a monolithic die, the focus is some differentiating feature, but the entire chip needs to be designed by a large team at the same time. When the design is split into chiplets, it allows an SoC designer to focus on their own area of expertise and further differentiate their solution with their own “secret-sauce” while relying on other experts from a growing ecosystem for the other pieces. Each portion of the SoC is expertly designed, possibly at a different time and location, by a different set of people, leading to a complete SiP (since the system is now in a package) with overall better power, performance, and area (PPA) metrics and faster time to market.

Conclusion

The move to chiplet-based designs is unmistakable. With larger, more powerful designs needed in every aspect of semiconductor use, be it AI, HPC, Automotive, or even consumer (physical AI), the industry is seeing a tremendous growth in chiplet-based designs. The benefits, as covered in this blog, are multi-faceted, from the technical challenges to the business feasibility. As chiplet technology continues to evolve, its ability to optimize costs, improve yields, enable greater customization, and accelerate time to market makes it a compelling choice for the future of semiconductor design.

In the next blog, we will look at the value of an open specification in the creation of a thriving chiplet ecosystem. Follow the UCIe Consortium via LinkedIn for updates.