By Stefan Rusu
Senior Director, TSMC IEEE Fellow
Why chiplets?
Advanced processors use chiplet design style to improve performance and reduce cost. Chiplets have three major benefits. First is the ability to pack multiple chiplets in the same package with good yields and performance while having a total silicon area that significantly exceeds the maximum reticle size of a single monolithic die. The second is the ability to choose the optimum technology node and design style for each functional chiplet. The third is the opportunity to mix-and-match the numbers and types of chiplet for flexibility in both product management and time to market benefit.
Figure 1[1] illustrates all these benefits using the AMD 4th Gen EPYC CPU package photo. There are 12 compute chiplets built in TSMC N5 process node and one I/O die (in the center) using the TSMC N6 technology. Since the I/O circuits don’t scale well to advanced nodes and they require higher operating voltages, it makes sense to keep them on the mature, lower cost N6 technology.
Figure 1 – Existingchiplet design (courtesyof AMD)
UCIe Implementation Options
The UCIe specification provides high-speed, low-latency communication between chiplets. The UCIe 1.0 specification targets 2D and 2.5D chiplet integration with support for multiple package options. The standard package uses organic substrates to connect multiple chiplets using metal traces similar to printed circuit boards. Channel lengths extend up to 25mm and energy efficiency is 0.5-1pJ/bit, depending on the voltage and frequency. The advanced package uses silicon interposers or bridges to enable finer pitches and shorter channels up to 2mm in length to improve energy efficiency to 0.25-0.5pJ/bit, depending on the voltage and frequency.
Advanced packages already support multiple die attach options, including Chip-on-Wafer-on-Substrate (CoWoS®) and Integrated Fan-Out (InFO). Power delivery can be enhanced with integrated voltage regulators and decoupling capacitors[2] as shown in the example in Figure 2. Design tools and flows are ready today, including physical design, extraction, signal and power integrity and thermal modeling.
Figure 2 – Packagetechnology example integrating multiple chiplets and power delivery[2]
Next steps
UCIe is an open industry standard that establishes an open chiplet ecosystem and ubiquitous interconnect at the package level. We expect to see a chiplet marketplace developing in the next few years that enables integrators to construct systems-in-package using building blocks sourced from multiple chip vendors. This will increase design productivity and reduce costs. However, UCIe will not stop here. Future UCIe versions are expected to add support for 3D-stacked chiplets and optical interfaces.
3D stacked interfaces connect multiple chiplets vertically to further reduce the interconnect trace length and area footprint. A popular partition will have cache and I/O circuits in one die and compute or graphics cores in the other[3]. The UCIe standard interconnect bus will enable integrators to combine chiplets from multiple vendors.
SerDes-based interconnects will be replaced by optical I/O’s in the future in order to reduce power and increase reach. UCIe interfaces over fiber or optical waveguides are already envisioned by several industry leaders[4]. Having a standard approach will increase design productivity and reduce the time- to-market.
References:
[1] AMD EPYC 9004 (Genoa)package photo
[2] F. Lee, et al., "Heterogeneous System-Level Package Integration — Trends and Challenges," 2020 IEEE Symposium on VLSI Technology.
[3] US patent9,514,093 – Methodand apparatus for stacking core and uncoredies having landingslots, https://patents.google.com/patent/US9514093B2
[4] H. Hsia et al., “Heterogeneous Integration of a Compact Universal Photonic Engine for Silicon Photonics Applications in HPC,” 2021 IEEE Electronic Components and Technology Conference (ECTC).
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